This invention relates to the processing of silicon wafers and, more particularly, to processes for reducing the surface roughness of silicon wafers by a combination of polishing and thermal annealing of the wafers.
Nearly all microelectronic devices are built upon silicon substrates or semiconductor “chips”. Device manufacturers produce the substrates by cutting the chips from silicon wafers. Silicon wafer suppliers most commonly prepare the wafers by slicing them from single crystal silicon ingots prepared by the Czochralski method. The Czochralski method involves drawing single crystal silicon from melted polycrystalline silicon by pulling a seed crystal brought into contact with the molten polycrystalline silicon.
In order to produce increasingly complex semiconductor devices, device manufacturers require smoother wafers. Many applications require “Grade 1” wafers. Grade 1 wafers typically possess a surface roughness of less than 1.5 Å as measured with a scan size of about 1 μm×about 1 μm and less than about 100 localized light scatterers above a size of about 65 nm per wafer.
Surface roughness is often measured by an atomic force microscope. An atomic force microscope operates by measuring the attraction or repulsion between a probe and the sample and correlating it to a distance. Surface roughness is often expressed as a statistical parameter, typically the arithmetic mean (Ra) or root mean square (RMS or Rq) average of the height deviations from the mean line. As used herein, surface roughness is expressed as the root mean square (RMS) unless indicated otherwise. The significance of the surface roughness measurement varies with the scan size of the atomic force microscope. Scan sizes of about 1 μm×about 1 μm or less generally correspond to shorter wavelength roughness while scan sizes of about 10 μm×about 10 μm or more generally correspond to longer wavelength roughness.
To achieve Grade 1 surface roughness specifications many silicon wafer manufacturers “rough” polish the wafer and then perform a “finish” polish (synonymously “mirror” polish) on the wafer. As can be seen from the lines referenced as “Rough” in FIG. 1 and in FIG. 2, a rough polish reduces the surface roughness of the wafer as measured with scan sizes of about 1 μm×about 1 μm to about 100 μm×about 100 μm to as low as about 1.5 Å and, more typically, to as low as about 1.9 Å. At shorter wavelengths a rough polish might reduce the surface roughness to less than about 2 Å as measured by scan sizes of about 0.1 μm×about 0.1 μm to about 1 μm×about 1 μm. Rough polishing uses a more potent chemistry as compared to finish polishing and results in removal of about 1 μm to about 20 μm and, more typically, from about 5 μm to about 15 μm of material from the surface of the wafer.
As can be seen from FIG. 1 and FIG. 2, a finish polish reduces the surface roughness of the wafer from the level obtained by rough polishing to about 1.7 Å to about 1.0 Å as measured by scan sizes of about 1 μm×about 1 μm to about 30 μm×about 30 μm. Finish polishes use a more dilute chemistry than rough polishes and remove only about 0.5 μm or less of material from the surface layer.
Finish polishing is generally costly and requires much processing time. A need exists for methods which reduce or eliminate finish polishing but which result in wafers with satisfactory short and long wavelength surface roughness.